Method for forming a semiconductor connection with a top surface having an enlarged recess

ABSTRACT

A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. patent application Ser. No. 08/595,834, filed Feb. 2, 1996.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not. Applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed generally to semiconductor interconnections and a method for forming a semiconductor interconnect, such as a via or a contact, having an enlarged recess on its top surface.

2. Description of the Background

It is well known in the semiconductor art to use interconnects, known as vias and contacts, to connect an upper conductor of current, such as metal or polysilicon, through a dielectric layer to a lower conductor of current. A via is an electrical connection between two metal layers, and a contact, in contrast, is an electrical connection between anything other than two metal layers, such as between metal and silicon. Vias and contacts are used extensively in very large scale integrated circuits, with an average circuit containing 16 million vias and contacts.

Vias and contacts are formed by an opening in a dielectric layer and a conductor within the opening. Directional deposition methods, such as evaporation and sputtering, are often used to deposit the conductor within the opening. Such methods, however, often provide poor step coverage and only a thin conductive layer on the vertical wall of the opening. Thin layers are often not sufficient to provide good electrical contact between the upper and lower conductors, and result in a high resistance and a propensity for electromigration failures.

The problem of poor step coverage is exaggerated as the size of opening shrinks, and the aspect ratio increases. As the diameter of an opening approaches one micron, the aspect ratio typically approaches 1 to 1. To reliably obtain good electrical connection, the opening is usually partially or entirely filled with a conductor, known as a “plug”.

Prior art methods for forming a plug typically include tapering the top edge of the opening, followed by the formation of the plug in the opening, and concluding with a hydrofluoric acid bath. The tapering of the top edge is often accomplished with a sputter etch, and the purpose was to increase the surface area of the plug formed within the opening. The acid bath is used to clean the top surface of the dielectric layer, but it also dissolves some of the material at the interface between the plug and the dielectric layer, creating a small recess several hundred Angstroms deep around the top edge of the plug.

The prior art methods have several shortcomings, such as poor metal coverage over the interconnect due to the small recess, which often contains impurities that increase the contact resistance, and which may develop into a latent defect.

The latent defect may take the form of erosion of a top level conductor deposited on the recess, and can be triggered if contaminants in the recess are exposed to moisture in a subsequent processing step. In addition, residuals left on the surface of the wafer after the plug is formed may cause shorts between conductors on the wafer surface. Those residuals are often not removed by the hydrofluoric acid bath used in the prior art. Furthermore, when a sputter etch is used to taper the corners of the opening, particles sputtered from the top edge of the opening end up in the bottom of the opening. These are particles of the dielectric layer, so they are not good conductors of current, and they increase the contact resistance at the bottom of the opening. Additionally, silicon regions are often the lower conductor of an interconnect, and it is well known that sputtering damages and causes leakage in silicon. As a result, the prior art methods either risk damaging the silicon regions, or require several additional process steps to provide a protective coating on silicon prior to the sputtering, and to remove the protective coating after the sputtering.

Defects occur in about 1 in every 100 million contacts. Since the average semiconductor device contains about 16 million contacts, a defect may be expected in more than one in every seven devices. The defects may be a latent defect caused by contamination in the recess, poor contact or adhesion at the top of the connection, poor contact at the bottom of the connection caused, for example, by dielectric material present from the sputtering step, or damage to a silicon region at the bottom of the opening.

Thus, the need exists for an improved method of forming a connection having reduced contact resistance, improved contact adhesion, and decreased susceptibility to latent defects.

SUMMARY OF THE INVENTION

The present invention is directed generally to a method of forming a connection in an integrated circuit. The method includes the step of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface opposite the lower conductor. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening. The plug has an upper surface proximate the upper surface of the dielectric layer. An edge of the upper surface is adjacent to the dielectric layer. A recess is formed proximate the edge of the upper surface. The recess extends into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug.

The connection formed by the method of the invention is located within a dielectric layer of an integrated circuit, and is located between an upper conductor and a lower conductor. A conductive plug is located within the opening, with the plug having an upper surface proximate the upper conductor, and an upper edge where the upper surface is adjacent to the dielectric layer. A recess is located proximate the upper edge of the plug. The recess extends into both the plug and the dielectric layer.

The invention solves the above-mentioned shortcomings in the prior art by cleaning the recess of impurities, thereby reducing the risk of a latent defect. Furthermore, at the same time that the recess is formed, the edge of the upper surface may be tapered thereby increasing the surface area of the plug, increasing the adhesion by an upper conductor and decreasing the contact resistance. Finally, the invention eliminates the need for sputtering the dielectric layer prior to the formation of the plug, thereby eliminating a source of dielectric material in the bottom of the opening, and eliminating a potential source of damage to the lower conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures, wherein:

FIGS. 1-3 and 5-8 are cross sectional views of an integrated circuit at successive steps in a method of fabricating an interconnect according to an embodiment of the invention;

FIG. 4 illustrates an alternative embodiment; and

FIG. 9 illustrates a system in which the present invention may be employed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is to be understood that the figures have been simplified to illustrate only those aspects of an interconnect which are relevant, and some of the dimensions have been exaggerated to convey a clear understanding of the present invention, while eliminating, for the purpose of clarity, some elements normally found in an interconnect. Those of ordinary skill in the art will recognize that other elements are required to produce an interconnect. However, because such elements and process steps are well known in the art, and because they do not further aid in the understanding of the present invention, a discussion of such elements is not provided herein.

FIG. 1 is a cross-sectional view of a dielectric layer 2, a semiconductor layer 4, and an interface 6 between the dielectric layer 2 and the semiconductor layer 4. The dielectric layer 2 may be of any dielectric material, and in the described embodiment it is boro-phospho-silicate glass oxide (“BPSG oxide”). A lower conductor 8 is located in the semiconductor layer 2 adjacent to the interface 6, and may be any conductor of current, such as a doped semiconductor or a metal. In the described embodiment, the lower conductor 8 is an n+ doped semiconductor. The lower conductor 8 is patterned to form conductive paths as is known in the art. The dielectric layer 2, semiconductor layer 4, interface 6, and lower conductor 8 form a portion of an integrated circuit 10.

FIG. 2 is a cross-sectional view of the integrated circuit 10 after an opening 12 has been created in the dielectric layer 2. The opening 12 is defined by an inner wall 14 and extends from a top surface 16 of the dielectric layer 2 to the lower conductor 8. The formation of such an opening in a dielectric layer is well known in the prior art. For example, an anisotropic etch in a reactive ion etch (“RIE”) reactor, using CF₄+CHF₃ at between 10° C. and 40° C. may be used. Many other methods of forming an opening are known, such as using a combination of isotropic and anisotropic etches to create sloped side walls in a dielectric layer.

FIG. 3 is a cross-sectional view of the integrated circuit 10 after the deposition of a plug layer 20, which substantially fills the opening 12. Tungsten is preferred as the material for the plug layer 20 because it is easily deposited using a chemical vapor deposition (“CVD”) process. Any conductor of current, however, may form the material for the plug layer 20. Because tungsten does not readily adhere to oxides, which comprise the dielectric layer 2 in the preferred embodiment, a “glue” layer 22 is preferably deposited before the plug layer 20. In the preferred embodiment titanium is used as the glue layer 22 because it adheres well to oxides and it consumes silicon dioxide, forming titanium silicide which has a low resistance. The silicon dioxide may remain at the bottom 18 of the opening 12 from previous process steps, and if it is not removed, it will increase the contact resistance between a plug, described below, and the lower conductor 8.

Titanium may be deposited, for example, by using a chemical vapor deposition (“CVD”) process, preferably using a titanium-chloride chemistry, such as titanium and CFCl₃. Alternatively, titanium may be sputtered directly onto the opening 12. Because sputtered titanium often results in shadowing, a columniator may be utilized to provide a more uniform distribution.

An alternative glue layer is titanium silicide, deposited by a CVD process. Titanium silicide CVD produces a conformal layer of titanium silicide, yielding uniform metal layers along the vertical and horizontal surfaces in and around the opening 12. The titanium silicide CVD process uses titanium tetrachloride in conjunction with titanium and silicon gasses to produce the layer of titanium silicide. Titanium silicide, however, does not consume silicon dioxide as titanium does.

In addition to the glue layer 22, a barrier layer 24 is used in the preferred embodiment because tungsten reacts with silicon to cause “worm holes” in the silicon. Worm holes result in small voids in the silicon surface where the silicon has migrated into the tungsten, and they increase the contact resistance and can cause leakage in diodes built in the silicon substrate. As a result, the barrier layer 24 is preferably used to separate the tungsten layer 20 from any form of silicon, such as a doped silicon substrate. When both a glue layer 22 and a barrier layer 24 are used, both the glue layer 22 and the barrier layer 24 may coat the bottom 18 and the walls 14 of the opening 12, as shown in FIG. 3.

FIG. 4 shows an alternative embodiment wherein the glue layer 22 is deposited only on the bottom 18 of the opening 12, so that it will consume any silicon dioxide present on the lower conductor 8. The barrier layer 24, however, is deposited on both the walls 14 and the bottom 18 of the opening 12. The preferred barrier layer 24, titanium nitride, is suitable as both a “barrier” and a “glue”, and is deposited on top of the glue layer 22, to act as a barrier between tungsten and silicon, and on the walls 14 to act as a glue layer. Titanium nitride readily adheres to the titanium/titanium silicide glue layer 22, to the tungsten plug layer 20, and to the dielectric layer 2. It also forms an effective barrier between the tungsten plug 26 and silicon, and is conformal and easily deposited by a CVD process. The titanium nitride may also be deposited by annealing titanium in the presence of nitrogen or ammonia.

Regardless of the manner in which titanium nitride is deposited, an annealing step follows the deposition of the glue layer 22, preferably either immediately after the glue layer 22 is deposited, or after the barrier layer 24 is deposited. The annealing step is necessary for the titanium, which preferably comprises the glue layer 22, to effectively consume silicon dioxide.

The glue and barrier layers 22 and 24, of course, are preferably not used when the plug 26 does not react adversely with any other materials in the opening 12, and when the plug 26 adequately adheres to the wall 14 and bottom 18 of the opening. In fact, the glue and barrier layers 22 and 24 are not required to utilize the invention, but they are used in the preferred embodiment. A layer of titanium may always be used, however, to consume silicon dioxide from the bottom 18 of the opening 12.

FIG. 5 shows a cross-sectional view of the integrated circuit 10 after portions of the plug layer 20, glue layer 22, and barrier layer 24 have been removed, leaving a plug 26 having a top surface 28 and an edge 29. The edge 29 of the plug 26 is defined generally by the glue and barrier layers 22 and 24. The portions of the plug layer 20, glue layer 22, and barrier layer 24 may be removed, for example, by a dry etch process using a chlorine-based gas is used, such as chlorine gas, CCl₄, or HCl. Preferably, however, a chemical-mechanical polish (“CMP”), as described in U.S. Pat. No. 5,224,534 (“the '534 Patent”) issued to Yu et al., assigned to Micron Technology, Inc. and incorporated herein by reference, may be used to remove the top layer of tungsten and leave the top surface 28 of the plug 26 even with the top surface 16 of the dielectric layer 2.

FIG. 6 shows the integrated circuit 10 after being subjected to a cleaning step. The surface of the integrated circuit 10 is cleaned, for example, by a bath of hydrofluoric acid which cleans the surface 16 of the dielectric layer 2 and opens up a small recess 30 in the glue and barrier layers 22 and 24 around the edge 29 of the plug 26. The recess 30 has a. generally rectangular cross-section, is typically between 1,000 and 2,000 Angstroms deep, typically about 1,000 Angstroms wide, and will often contain impurities. As discussed above, if the impurities remain in the recess 30 they may develop into a latent defect which may ultimately cause a failure of the device. As described in the '534 Patent, the CMP process may also form a recess 30 at the edge 29 of the plug 26, without the use of a hydrofluoric acid bath.

Following the cleaning step, an “etchback” step is preferably performed which removes material from the top surface 28 of the plug 26 so that the plug 26 is between about 1,000 to 2,000 Angstroms below the top surface 16 of the dielectric layer 2. The etchback is to compensate for the different etch rates of tungsten and BPSG oxide, in anticipation of an etch step described below with respect to FIG. 7. The depth of the etchback is chosen so that at the conclusion of the etch step, discussed below with respect to FIG. 7, the top surface 28 of the plug 26 and the top surface 16 of the dielectric layer 2 are even. The etchback may be achieved, for example, through a dry etch of the plug 26.

FIG. 7 shows a cross section of the integrated circuit 10 after it is subjected to an etch step to clean and enlarge the recess 30. After the recess 30 is enlarged it extends into the dielectric layer 2 and the plug 26. Many types of etches, such as facet etches and sputter etches, may be used to clean and enlarge the recess 30. It has been found, however, that superior results are achieved with a sputter etch using an argon plasma, with a pressure between five and fifty millitorr, a flow rate of between 10 and 100 standard cubic centimeters per minute (“sccm”) of argon gas, a plasma energy level of between 1.7 and 5.1 watts per square centimeter of the target surface, and an angle between 40° and 60° above horizontal. In the most preferred embodiment, the sputter etch angle is 58° above horizontal. The sputter etch typically increases the width of the recess 30 from about 1,000 Angstroms to between about 2,000 Angstroms and 3,000 Angstroms, although the depth of the recess 30 is usually not significantly changed. Of course, both larger and smaller recesses 30 are possible, and the depth of the recess may be changed to suit particular needs by, for example, altering the sputter etch angle. When the sputter etch increases the width of the recess 30, it tapers the top surface 28 of the plug 26, which increases the surface area of the plug 26, and it tapers the top surface 16 of the dielectric layer 2. The increased surface area of the plug 26 allows for a lower resistance contact and better adhesion with a subsequently applied upper conductor. The tapered plug 26 and dielectric layer 2 also allow for very good step coverage over the recess 30 when a subsequent upper conductor layer is applied, as described below with respect to FIG. 8. The sputter etch also cleans the recess 30 of impurities and residue remaining from previous process steps, further reducing the likelihood of a latent defect. Furthermore, the sputter etch cleans the surface of the integrated circuit 10 of impurities and removes residue, such as tungsten particles deposited during the formation of the plug 26, which are often not removed in the cleaning step using hydrofluoric acid.

During the sputter etch step both the plug 26 and the dielectric layer 2 are etched, but because tungsten sputters more slowly than BPSG oxide, the thickness of the plug 26 decreases at a slower rate than the thickness of the dielectric layer 2. For that reason, in the preferred embodiment the top surface 28 of the plug 26 is etched back about 1,000 to 2,000 Angstroms below the top surface 16 of the dielectric layer 2 prior to the etch step. As a result of the etchback of the plug 26, at the conclusion of the sputter etch the top surface 28 of the plug 26 is approximately even with the top surface 16 of the dielectric layer 2.

FIG. 8 is a cross-sectional view of the integrated circuit 10 after a top conductor layer 32 has been applied to the top surface 16 of the dielectric layer 2 and the top surface 28 of the plug 26. The top conductor layer 32 fills the recess 30, taking advantage of the increased surface area of the plug 26, and resulting in a lower resistance contact and better contact adhesion. Good step coverage over the recess 30 results from the tapered plug 26 and dielectric layer 2. The top conductor layer 32 may be any conductor of current, such as aluminum, titanium, copper, or polysilicon, and methods of deposition of the top conductor layer 32 are well known in the prior art, such as by sputtering and CVD. The top conductor layer 32 is patterned to form conductive paths as is known in the art.

FIG. 9 illustrates a system 34 in which the present invention may be employed. The system is comprised of a solid state device, such as memory device 36, in which connections of the type disclosed herein are made. The memory device is under the control of a microprocessor 38 which may be programmed to carry out particular functions as is known in the art.

Those with ordinary skill in the art will recognize that many modifications and variations of the present invention may be implemented. For example, the recess 30 may be formed in a plug 26 and dielectric layer 2 without the presence of glue and barrier layers 22 and 24. The foregoing description and the following claims are intended to cover all such modifications and variations. 

What is claimed is:
 1. An interconnect between an upper conductor and a lower conductor, comprising: a dielectric layer between the upper conductor and the lower conductor, the dielectric layer having a sidewall defining an opening through the dielectric layer; and a conductive plug within the opening, the plug having a height and an upper surface, wherein the upper surface includes: a center portion in contact with the upper conductor; and an outer portion that tapers downwardly from the center portion to the sidewall of the dielectric such that the height of the conductive plug is a maximum at the center portion and a minimum at the sidewall of the dielectric, wherein the outer portion is in contact with the upper conductor at a plurality of points, wherein the plurality of points includes a point that is not common to the center portion and the outer portion.
 2. The interconnect of claim 1, wherein the center portion of the upper surface of the plug is in a plane parallel to a plane of an upper surface of the dielectric layer.
 3. The interconnect of claim 2, wherein the plane of the center portion of the upper surface of the plug is coplanar with the plane of the upper surface of the dielectric layer.
 4. The interconnect of claim 1, wherein the outer portion of the upper surface of the plug tapers to the sidewall of the dielectric layer at an angle between forty degrees and sixty degrees below horizontal.
 5. The interconnect of claim 4, wherein the outer portion of the upper surface of the plug tapers to the sidewall of the dielectric layer at an angle of fifty-eight degrees below horizontal.
 6. The interconnect of claim 1, wherein the dielectric layer has an upper surface that tapers to the sidewall.
 7. The interconnect of claim 6, wherein the upper surface of the dielectric layer tapers to the sidewall at an angle between forty and sixty degrees below horizontal.
 8. The interconnect of claim 7, wherein the upper surface of the dielectric layer tapers to the sidewall at an angle of fifty-eight degrees below horizontal.
 9. An interconnect between an upper conductor and a lower conductor, comprising: a dielectric layer between the upper conductor and the lower conductor, the dielectric layer having a sidewall defining an opening through the dielectric layer, and the dielectric layer having an upper surface that tapers to the sidewall; and a conductive plug within the opening, the plug having a height and an upper surface, wherein the upper surface includes: a center portion in contact with the upper conductor; and an outer portion that tapers downwardly from the center portion to the sidewall of the dielectric such that the height of the conductive plug is a maximum at the center portion and a minimum at the sidewall of the dielectric, wherein the outer portion is in contact with the upper conductor at a plurality of points, wherein the plurality of points includes a point that is not common to the center portion and the outer portion.
 10. The interconnect of claim 9, wherein the upper surface of the dielectric layer includes a non-tapered portion and the center portion of the upper surface of the plug includes a non-tapered center portion, and wherein the non-tapered portion of the upper surface of the dielectric layer is in a plane parallel to a plane of the non-tapered center portion of the upper surface of the plug.
 11. The interconnect of claim 10, wherein the plane of the non-tapered portion of the upper surface of the dielectric layer is coplanar with the plane of the non-tapered center portion of the upper surface of the plug.
 12. The interconnect of claim 9, wherein the upper surface of the dielectric layer and the outer portion of the upper surface of the plug taper to the sidewall at an angle between forty and sixty degrees below horizontal.
 13. The interconnect of claim 12, wherein the upper surface of the dielectric layer and the outer portion of the upper surface of the plug taper to the sidewall at an angle of fifty-eight degrees below horizontal. 